Cadence SPB OrCAD 16.60.028 Hotfix | 1.0 Gb
Cadence Design Systems Ltd., a world-renowned provider of EDA software, has released an hotfix 024 for Cadence SPB OrCAD 16.60, software a comprehensive package design of electronic circuits, analog and digital simulation, IC design of programmable logic and custom circuits, as well as the development and preparation for the production of printed circuit boards.
Cadence Design Systems, Inc., a leader in global electronic design innovation, launched the Cadence OrCAD 16.6 design solution with new features, enhanced customization capabilities, and 20 percent simulation performance improvements that provide customers a shorter, more predictable path to product creation.
This latest release offers numerous improvements to tool usability and performance, but at the heart of 16.6 are three key benefits: enhanced miniaturization capabilities, timing-aware physical implementation and verification for faster timing closure, and the industrys first electrical CAD team collaboration environment for PCB design using Microsoft SharePoint technology.
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CCRID PRODUCT PRODUCTLEVEL2 TITLE
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1199256 ALLEGRO_EDITOR INTERACTIV DFA bubble does not appear when moving a symbol to within another symbols dfa bounds on specific symbols
1220196 ALLEGRO_EDITOR OTHER create xsection chart results in ERROR(SPMHA1-73): Text line is outside of the extents.
1259520 ALLEGRO_EDITOR EDIT_ETCH Allegro will crash when adding connections to a differential pair.
1260446 ALLEGRO_EDITOR VALOR Creating odb output the xhatch shapes where arcs are will become inverted. Difference in the geoms.out extraction?
1261313 ALLEGRO_EDITOR INTERFACES Step mapping does not show all Available Packages
1261356 CONCEPT_HDL CREFER crefer is crashing with generate for all nets option
1261514 ALLEGRO_EDITOR ARTWORK Exporting raster artwork with overlaping voids fails.
1261735 ALLEGRO_EDITOR ARTWORK Presence of Smaller shapes inside bigger shapes is crashing artwork generation.
1262019 ALLEGRO_EDITOR INTERFACES Artwork control form hangs if we close PDF publisher gui
1262246 CONSTRAINT_MGR ANALYSIS Constraint manager shows ALL PASS when Adding members to a NetClass and adding parallelism rule
1262560 APD WIREBOND bondwire can't connect to GND ring directly
1263275 CONSTRAINT_MGR OTHER Import of constraint file hangs in this design
1263358 SIP_LAYOUT OTHER SiP Layout - Void adjacent Layer enhancement to merge voiding for PADS without changing shape params
1264109 ADW LRM LRM error - WARNING(SPDWREV-7): Unable to read the design
1265580 APD MANUFACTURING Icp_soldermask_allow_pins cannot create correct solder mask when the pin rotate.
1266391 APD LOGIC SPB16.6 Derive assignment : want to select 1 DRC marker only.
1266687 ALLEGRO_EDITOR SKILL The SKILL p
1267267 SIP_LAYOUT WIZARDS Attempting to create a die using the die text in wizard but the tool is not creating the correct die outline
1267308 SIP_LAYOUT OTHER When updating a BGA with the Symbol Spreadsheet tool it will start, update a few pins then stop.
1267639 ALLEGRO_EDITOR PARTITION Allegro crashes when partition is created and opened from a location that contains "!" in its path.
1267704 SIP_LAYOUT STREAM_IF Cannot import stream file, the tool starts scanning the file and never stops.
1267907 CONCEPT_HDL CORE Ctrl+RMB Context Menu Option doesn't work.
About Cadence Design Systems, Inc.
Cadence enables global electronic design innovation and plays an essential role in the creation of today's integrated circuits and electronics. Customers use Cadence software, hardware, IP, and services to design and verify advanced semiconductors, consumer electronics, networking and telecommunications equipment, and computer systems. The company is headquartered in San Jose, Calif., with sales offices, design centers, and research facilities around the world to serve the global electronics industry.
Name: Cadence SPB OrCAD
Version: (32bit) 16.60.028 Hotfix
Home: www.cadence.com
Interface: english
OS: Windows XP / Vista / Seven / 8
System Requirements: Cadence SPB OrCAD 16.60.000 - 16.60.027
Size: 1.0 Gb
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