Cadence Design Systems, Inc., a leader in global
electronic design innovation, launched the Cadence OrCAD 16.6 design
solution with new features, enhanced customization capabilities, and 20
percent simulation performance improvements that provide customers a
shorter, more predictable path to product creation.
This latest
release offers numerous improvements to tool usability and performance,
but at the heart of 16.6 are three key benefits: enhanced
miniaturization capabilities, timing-aware physical implementation and
verification for faster timing closure, and the industry’s first
electrical CAD team collaboration environment for PCB design using
Microsoft SharePoint technology.
A hot fix is a software
maintenance package containing a small number of code fixes, designed to
fix a sall number of critical problems. A hot fix enables a customer to
receive fixes for urgent problems, without having to wait for the next
service pack.
Each successive Fix Pack is comprehensive and
contains the material from the earlier Fix Packs for that Release, as
well as all Interim Fixes made available since the previous Fix Pack or
full Release. In other words, when multiple Fix Packs are available, you
would not need to apply Fix Pack 1 before applying Fix Pack 2.
DATE: 10-25-2013 HOTFIX VERSION: 018=====================================================================================
CCRID PRODUCT PRODUCTLEVEL2 TITLE
======================================================================================
1118303 CONCEPT_HDL CONSTRAINT_MGR can not prdefine default units in HDL
1174901
ALLEGRO_EDITOR GRAPHICS Spurious odd lines are shown in shapes
and text that are not part of the design with opengl
1176990 CONCEPT_HDL OTHER DEHDL BOM tool doesn?t see similar names.
1179665 GRE CORE Plan Topological Crashes after around 8 hours of routing.
1188193 CONCEPT_HDL CHECKPLUS CheckPlus not recognizing PIN as a base object.
1189100 SCM OTHER Replace part in SCM using ADW as library fails
1189507 SCM SCHGEN ERROR(SPCOCN-2009): Package error after second schgen run with Preserve mode.
1192391 CONSTRAINT_MGR CONCEPT_HDL Restore from definition deletes local objects in other blocks
1194597 FSP OTHER Pin definition problem
1195202 SIP_LAYOUT LEFDEF_IF Cannot add .lef files in IC Library Manager. Getting warning message WARNING(SPMHLD-52)
1195309 GRE CORE GRE crashing during Plan Spatial.
1197262 ALLEGRO_EDITOR MANUFACT Angular Dimension created in symbol is placed w.r.t. board origin and angle is blank
1198521 CONCEPT_HDL OTHER Cadence DEHDL issue - Note for Hotfix_SPB16.60.016_wint_1of1
1199219
ALLEGRO_EDITOR INTERFACES Question on STEP Model export which
uses PLACE_BOUND layer for any symbols that do not have STEP model
mapped
1199235 ALLEGRO_EDITOR SCHEM_FTB capture's behavior is redundant while creating pcb editor netlist
1199323 GRE IFP_INTERACTIVE Crash when importing logic
1199368 SIP_LAYOUT DIE_EDITOR Refresh of die abstract in die editor with this design takes over two hours
1199760 ALLEGRO_EDITOR DATABASE Allegr won't display Soldermask Top layer
About Cadence Design Systems, Inc.Cadence
enables global electronic design innovation and plays an essential role
in the creation of today's integrated circuits and electronics.
Customers use Cadence software, hardware, IP, and services to design and
verify advanced semiconductors, consumer electronics, networking and
telecommunications equipment, and computer systems. The company is
headquartered in San Jose, Calif., with sales offices, design centers,
and research facilities around the world to serve the global electronics
industry.
Name: Cadence SPB OrCAD
Version: (32bit) 16.60.018 Hotfix
Home: www.cadence.com
Interface: english
OS: Windows XP / Vista / Seven
System Requirements: Cadence SPB OrCAD 16.60.000 - 16.60.017
Size: 873.2 mb
